1. Field of the Invention
The present invention relates to a technique for performing phase adjustment among clock signals in a semiconductor integrated circuit.
2. Description of the Related Art
A semiconductor integrated circuit is used in an information processing apparatus such as a personal computer (PC), and an image forming apparatus such as a multifunction peripheral (MFP). In general, the semiconductor integrated circuit used in these apparatuses includes therein a bus structure for data transfer between a central processing unit (CPU) and various peripheral functional circuits. Such a bus in the semiconductor integrated circuit has a configuration where a flip-flop (FF) synchronous circuit that operates in synchronization with a clock signal is used to receive and transmit data, so that the semiconductor integrated circuit performs data transfer using the synchronous bus. In synchronous circuit design, the circuit design is performed assuming a configuration in which the edges of clock signals are coincident with each other, so that the timing design for guaranteeing the circuit operation by verifying the setup time and the hold time of an FF is performed. In addition, in a semiconductor integrated circuit that uses a plurality of clock signals, the normal operations of synchronous circuits can be guaranteed by satisfying the timing design in the cycle of a faster clock signal if clock signals that operate FFs has a relationship in which the ratio of the frequency of a clock signal and the frequency of another clock signal can be expressed as the ratio of natural numbers and their edge positions are coincident with each other. Conversely, in the case of data transfer between clock signals having the same frequency but the phases shifted from each other, it is more difficult to secure the setup time and the hold time of an FF that receives data. Accordingly, for the synchronization circuits, it is important that the phases of clock signals are coincident with each other.
For example, Japanese Patent Application Laid-Open No. 2009-117020 discloses a technique in which, by detecting the phases of two types of clock signals having the same frequency but the phases shifted from each other by a half cycle, and inserting a delay into either of the clock signals to adjust the phases, the phases of the two types of clock signals are made coincident with each other.
The technique disclosed in Japanese Patent Application Laid-Open No. 2009-117020 is limited to a configuration that adjusts the phases of two types of clock signals having the same frequency but the phases shifted from each other by a half cycle. Some semiconductor integrated circuits used in various devices may use more types of clock signals. In this case, it is necessary to adjust the phases of two or more types of clock signals having different frequencies so that the phases can be synchronized with one another.
In a case where, to synchronize the phases of two or more types of clock signals with one another, the phases need to be adjusted so that the edges of the clock signals are coincident with one another as described above, by performing the phase adjustment relative to the lowest-frequency clock signal, the edges of the clock signals having the other frequencies can also be made coincident. However, in the case of implementing the above phase adjustment by inserting a delay into a clock signal, the delay needs to be inserted into the clock signal having the lowest frequency, i.e., the longest cycle, resulting in a longer time taken to perform the adjustment.